MPC8349VVAGF View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

MFG CO.

MPC8349VVAGF

PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications

Freescale Semiconductor 

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Ethernet: Three-Speed Ethernet, MII Management

Figure 13 shows the TBI receive AC timing diagram.

tTRX

tTRXR

PMA_RX_CLK1

tTRXH

tTRXF

RCG[9:0]

Even RCG Odd RCG

tTRDVKH

tSKTRX

tTRDXKH

PMA_RX_CLK0

tTRXH

tTRDXKH

tTRDVKH

Figure 13. TBI Receive AC Timing Diagram

8.2.4 RGMII and RTBI AC Timing Specifications

Table 27 presents the RGMII and RTBI AC timing specifications.

Table 27. RGMII and RTBI AC Timing Specifications

At recommended operating conditions with LVDD of 2.5 V ± 5%.

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

Data to clock output skew (at transmitter)

Data to clock input skew (at receiver)2

Clock cycle duration3

Duty cycle for 1000Base-T4, 5

Duty cycle for 10BASE-T and 100BASE-TX3, 5

tSKRGT

–0.5

—

tSKRGT

1.0

—

tRGT

7.2

8.0

tRGTH/tRGT

45

50

tRGTH/tRGT

40

50

0.5

ns

2.8

ns

8.8

ns

55

%

60

%

Rise time (20%–80%)

tRGTR

—

—

0.75

ns

Fall time (20%–80%)

GTX_CLK125 reference clock period

tRGTF

tG126

—

—

0.75

ns

—

8.0

—

ns

GTX_CLK125 reference clock duty cycle

tG125H/tG125

47

—

53

%

Notes:

1. In general, the clock reference symbol for this section is based on the symbols RGT to represent RGMII and RTBI timing. For

example, the subscript of tRGT represents the TBI (T) receive (RX) clock. Also, the notation for rise (R) and fall (F) times

follows the clock symbol. For symbols representing skews, the subscript is SK followed by the clock being skewed (RGT).

2. This implies that PC board design requires clocks to be routed so that an additional trace delay of greater than 1.5 ns is added

to the associated clock signal.

3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.

4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet clock domains as long

as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned.

5. Duty cycle reference is LVDD/2.

6. This symbol represents the external GTX_CLK125 and does not follow the original symbol naming convention.

MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10

28

Freescale Semiconductor

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