MPC8541CPXAJD View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

MFG CO.

MPC8541CPXAJD

PowerQUICC™ III Integrated Communications Processor Hardware Specifications

Freescale Semiconductor 

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CPM

Table 33. CPM Input AC Timing Specifications 1 (continued)

Characteristic

Symbol 2

Min3

Unit

PIO inputs—input hold time

tPIIXKH

1

ns

COL width high (FCC)

tFCCH

1.5

CLK

Notes:

1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings

are measured at the pin.

2. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)

(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tFIIVKH

symbolizes the FCC inputs internal timing (FI) with respect to the time the input signals (I) reaching the valid state (V)

relative to the reference clock tFCC (K) going to the high (H) state or setup time.

3. PIO and TIMER inputs and outputs are asynchronous to SYSCLK or any other externally visible clock. PIO/TIMER inputs

are internally synchronized to the CPM internal clock. PIO/TIMER outputs should be treated as asynchronous.

Table 34. CPM Output AC Timing Specifications 1

Characteristic

Symbol 2

Min

Max

Unit

FCC outputs—internal clock (NMSI) delay

tFIKHOX

1

5.5

ns

FCC outputs—external clock (NMSI) delay

tFEKHOX

2

8

ns

SPI outputs—internal clock (NMSI) delay

tNIKHOX

0.5

10

ns

SPI outputs—external clock (NMSI) delay

tNEKHOX

2

8

ns

PIO outputs delay

tPIKHOX

1

11

ns

Notes:

1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings

are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tFIKHOX symbolizes the FCC

inputs internal timing (FI) for the time tFCC memory clock reference (K) goes from the high state (H) until outputs (O) are

invalid (X).

Figure 23 provides the AC test load for the CPM.

Output

Z0 = 50 Ω

RL = 50 Ω

OVDD/2

Figure 23. CPM AC Test Load

MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2

Freescale Semiconductor

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