MPC8541CPXAJD View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
MPC8541CPXAJD
Freescale Semiconductor
'MPC8541CPXAJD' PDF : 84 Pages View PDF
I2C
Figure 35 provides the test access port timing diagram.
JTAG
External Clock
VM
TDI, TMS
TDO
tJTKLOX
tJTKLOV
tJTIVKH
VM
Input
Data Valid
tJTIXKH
Output Data Valid
TDO
tJTKLOZ
Output Data Valid
VM = Midpoint Voltage (OVDD/2)
Figure 35. Test Access Port Timing Diagram
12 I2C
This section describes the DC and AC electrical characteristics for the I2C interface of the MPC8541E.
12.1 I2C DC Electrical Characteristics
Table 39 provides the DC electrical characteristics for the I2C interface of the MPC8541E.
Table 39. I2C DC Electrical Characteristics
At recommended operating conditions with OVDD of 3.3 V ± 5%.
Parameter
Symbol
Min
Max
Unit Notes
Input high voltage level
Input low voltage level
Low level output voltage
Output fall time from VIH(min) to VIL(max) with a bus
capacitance from 10 to 400 pF
VIH
0.7 × OVDD
OVDD+ 0.3
V
—
VIL
–0.3
0.3 × OVDD
V
—
VOL
0
0.2 × OVDD
V
1
tI2KLKV 20 + 0.1 × CB
250
ns
2
Pulse width of spikes which must be suppressed by the
tI2KHKL
0
input filter
50
ns
3
Input current each I/O pin (input voltage is between 0.1 ×
II
–10
OVDD and 0.9 × OVDD(max)
10
μA
4
Capacitance for each I/O pin
CI
—
10
pF
—
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. CB = capacitance of one bus line in pF.
3. Refer to the MPC8555E PowerQUICC™ III Integrated Communications Processor Reference Manual for information on the
digital filter used.
4. I/O pins obstruct the SDA and SCL lines if OVDD is switched off.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
50
Freescale Semiconductor
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