MPC8541CPXAJD View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

MFG CO.

MPC8541CPXAJD

PowerQUICC™ III Integrated Communications Processor Hardware Specifications

Freescale Semiconductor 

Prev 41 42 43 44 45 46 47 48 49 50 Next

JTAG

Figure 31 provides the AC test load for TDO and the boundary-scan outputs of the MPC8541E.

Output

Z0 = 50 Ω

RL = 50 Ω

OVDD/2

Figure 31. AC Test Load for the JTAG Interface

Figure 32 provides the JTAG clock input timing diagram.

JTAG

External Clock

VM

VM

VM

tJTKHKL

tJTG

tJTGR

VM = Midpoint Voltage (OVDD/2)

Figure 32. JTAG Clock Input Timing Diagram

Figure 33 provides the TRST timing diagram.

tJTGF

TRST

VM

VM

tTRST

VM = Midpoint Voltage (OVDD/2)

Figure 33. TRST Timing Diagram

Figure 34 provides the boundary-scan timing diagram.

JTAG

External Clock

Boundary

Data Inputs

Boundary

Data Outputs

Boundary

Data Outputs

VM

tJTKLDX

tJTKLDV

tJTDVKH

VM

Input

Data Valid

tJTDXKH

Output Data Valid

tJTKLDZ

Output Data Valid

VM = Midpoint Voltage (OVDD/2)

Figure 34. Boundary-Scan Timing Diagram

MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2

Freescale Semiconductor

49

Share Link: