CPM
Figure 24 through Figure 29 represent the AC timing from Table 33 and Table 34. Note that although the
specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when
the falling edge is the active edge.
Figure 24 shows the FCC internal clock.
BRG_OUT
FCC Input Signals
tFIIVKH
tFIIXKH
FCC Output Signals
(When GFMR TCI = 0)
tFIKHOX
FCC Output Signals
(When GFMR TCI = 1)
tFIKHOX
Figure 24. FCC Internal AC Timing Clock Diagram
Figure 25 shows the FCC external clock.
Serial CLKIN
FCC Input Signals
tFEIVKH
tFEIXKH
FCC Output Signals
(When GFMR TCI = 0)
tFEKHOX
FCC Output Signals
(When GFMR TCI = 1)
tFEKHOX
Figure 25. FCC External AC Timing Clock Diagram
Figure 26 shows Ethernet collision timing on FCCs.
COL
(Input)
tFCCH
Figure 26. Ethernet Collision AC Timing Diagram (FCC)
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
44
Freescale Semiconductor