Clocking
15 Clocking
This section describes the PLL configuration of the MPC8541E. Note that the platform clock is identical
to the CCB clock.
15.1 Clock Ranges
Table 44 provides the clocking specifications for the processor core and Table 44 provides the clocking
specifications for the memory bus.
Table 44. Processor Core Clocking Specifications
Maximum Processor Core Frequency
Characteristic
533 MHz
600 MHz
667 MHz
833 MHz
1000 MHz Unit Notes
Min Max Min Max Min Max Min
Max
Min
Max
e500 core
processor
frequency
400 533 400 600 400 667
400
833
400
1000 MHz 1, 2, 3
Notes:
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to Section 15.2, “Platform/System PLL Ratio,” and Section 15.3, “e500 Core PLL Ratio,” for ratio settings.
2.)The minimum e500 core frequency is based on the minimum platform frequency of 200 MHz.
3. 1000 MHz frequency supports only a 1.3 V core.
Table 45. Memory Bus Clocking Specifications
Characteristic
Maximum Processor Core
Frequency
533, 600, 667, 883, 1000 MHz
Unit
Notes
Min
Max
Memory bus frequency
100
166
MHz
1, 2, 3
Notes:
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that
the resulting SYSCLK frequency, e500 (core) frequency, and CCB frequency do not exceed their
respective maximum or minimum operating frequencies. Refer to Section 15.2, “Platform/System PLL
Ratio,” and Section 15.3, “e500 Core PLL Ratio,” for ratio settings.
2. The memory bus speed is half of the DDR data rate, hence, half of the platform clock frequency.
3. 1000 MHz frequency supports only a 1.3 V core.
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
64
Freescale Semiconductor