MPC8541CPXAJD View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
MPC8541CPXAJD
Freescale Semiconductor
'MPC8541CPXAJD' PDF : 84 Pages View PDF
Clocking
15.3 e500 Core PLL Ratio
Table 47 describes the clock ratio between the e500 core complex bus (CCB) and the e500 core clock. This
ratio is determined by the binary value of LALE and LGPL2 at power up, as shown in Table 47.
Table 47. e500 Core to CCB Ratio
Binary Value of LALE, LGPL2 Signals Ratio Description
00
2:1 e500 core:CCB
01
5:2 e500 core:CCB
10
3:1 e500 core:CCB
11
7:2 e500 core:CCB
15.4 Frequency Options
Table 48 shows the expected frequency values for the platform frequency when using a CCB to SYSCLK
ratio in comparison to the memory bus speed.
Table 48. Frequency Options with Respect to Memory Bus Speeds
CCB to SYSCLK
Ratio
SYSCLK (MHz)
17
25
33
42
67
83
100
111
133
Platform/CCB Frequency (MHz)
2
200
222
267
3
200
250
300
333
4
267
333
5
208
333
6
200
250
8
200
267
333
9
225
300
10
250
333
12
200
300
16
267
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
66
Freescale Semiconductor
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