MSM5718B70 View Datasheet(PDF) - Oki Electric Industry
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MFG CO.
'MSM5718B70' PDF : 40 Pages View PDF
¡ Semiconductor
MSM5718B70
RDRAM OPERATION
The RDRAM is composed of two independent banks of memory with each bank storing a full 1
Mbyte of data (see Fig. 13). Each of these banks has a 2KByte open page associated with it that is built
out of sense amplifier arrays. These sense amplifiers hold the last accessed row of their associated
bank in the sense amplifiers. This allows further accesses to the same row of memory to result in page
hits. With the row already stored in the sense amplifiers, subsequent data can be accessed with very
low latency. Each RDRAM added to a system adds two open pages to the memory system helping
to increase hit rates.
A page miss results when a row is accessed that is not currently stored as one of the open pages. When
this happens, the requesting master is sent a NACK Acknowledge packet indicating the requested
row is not yet available. The RDRAM then loads the requested row into the sense amplifiers and
waits for the master to submit a retry of the previous request. Fig. 11 shows an example of a read miss
followed by a read hit for a 32 byte memory read operation.
The amount of time that is needed before the retry can be serviced depends on whether the data in
the open page is clean or dirty. The sense amplifiers act as a "write back" cache in that data written
to the open page is not written into the actual DRAM cells until the page is closed. If the data in an
open page is clean (not previously written) when a new page is requested, the open page does not
need to be written back into the DRAM. If the data in an open page is dirty, then additional time must
be added to the miss retry delay to account for the writeback operation.
ADDRESS MAPPING
Address mapping hardware is provided to increase page hit rates by allowing system designers to
easily perform n-way RDRAM interleaving. In a non-interleaved memory system, contiguous
blocks of addresses follow each other in sequence in one RDRAM, which is then followed by the next
RDRAM.
Using address mapping, adjacent blocks of data (2K or greater) can be separated across several
RDRAMs, and therefore across several open pages. This allows a more optimal mapping of the pages
as caches and creates higher effective page hit rates. In a typical system containing, for example eight
RDRAMs, hit rates could be expected to be as high as 95%. Address mapping is easily adjusted by
writing a control register in each RDRAM.
TRANSACTION CONCURRENCY
Concurrent transactions can be used to optimize RDRAM utilization in high performance applications
by taking advantage of available channel bandwidth during page miss latency periods. When a miss
in one RDRAM takes place, that device will be busy loading a new row into one of its sense amp
caches. The channel and all other RDRAMs will still be available for use. While waiting for the first
RDRAM to finish loading its open page, a transaction to another RDRAM can be initiated. In systems
where memory accesses can be queued, a tansaction can take place for any pending access residing
in a different RDRAM.
Pretouching can be used in systems where certain memory accesses are predictable, such as video
applications. This is done when an application is finished with a particular RDRAM and about to
access a different one. If the next access to an RDRAM is known in advance, a transaction can be first
generated that will cause a row miss and prepare the RDRAM for its next access. When the device
is next accessed, the required row of data will already be loaded in the open page and a page hit will
take place.
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