2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
FLASH WRITE CYCLE TIMING REQUIREMENTS
PARAMETER
Reset HIGH recovery to WE# going LOW
CE# setup to WE# going LOW
Write pulse width
Data setup to WE# going HIGH
Address setup to WE# going HIGH
CE# hold from WE# HIGH
Data hold from WE# HIGH
Address hold from WE# HIGH
Write pulse width HIGH
WP# setup to WE# going HIGH
VPP setup to WE# going HIGH
Write recovery before READ
WP# hold from valid SRD
VPP hold from valid SRD
WE# HIGH to data valid
SYMBOL
tRS
tCS
tWP
tDS
tAS
tCH
tDH
tAH
tWPH
tRHS
tVPS
tWOS
tRHH
tVPH
tWB
-10/-11
VCC = 1.65V–1.95V or
1.80V–2.20V
MIN
150
0
50
50
50
0
0
9
30
200
200
50
0
0
MAX
tAA+50
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FLASH ERASE AND PROGRAM CYCLE TIMING REQUIREMENTS
PARAMETER
4KW parameter block program time
32KW parameter block program time
Word program time
4KW parameter block erase time
32KW parameter block erase time
Program suspend latency
Erase suspend latency
-10/-11
VCC = 1.65V–1.95V or
1.80V–2.20V
TYP
MAX
0.1
0.3
0.8
2.4
8
185
1
4
1.5
5
5
10
5
20
UNITS
s
s
µs
s
s
µs
µs
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02
34
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.