MT28F008B5VG-8T View Datasheet(PDF) - Micron Technology
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MFG CO.
'MT28F008B5VG-8T' PDF : 30 Pages View PDF
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SMART 5 BOOT BLOCK FLASH MEMORY
COMMAND EXECUTION
Commands are issued to bring the device into dif-
ferent operational modes. Each mode allows specific
operations to be performed. Several modes require a
sequence of commands to be written before they are
reached. The following section describes the proper-
ties of each mode, and Table 3 lists all command
sequences required to perform the desired operation.
Read Array
The array read mode is the initial state of the device
upon power-up and after a RESET. If the device is in
any other mode, READ ARRAY (FFh) must be given to
return to the array read mode. Unlike the WRITE
SETUP command (40h), READ ARRAY does not need
to be given before each individual read access.
IDENTIFY DEVICE
IDENTIFY DEVICE (90h) may be written to the CEL
to enter the identify device mode. While the device is
in this mode, any READ produces the device ID when
A0 is HIGH and the manufacturer compatibility ID
when A0 is LOW. The device remains in this mode until
another command is given.
Write Sequence
Two consecutive cycles are needed to input data to
the array. WRITE SETUP (40h or 10h) is given in the
first cycle. The next cycle is the WRITE, during which
the write address and data are issued and VPP is
brought to VPPH. Writing to the boot block also
requires that the RP# pin be brought to VHH or the WP#
pin be brought HIGH at the same time VPP is brought
to VPPH. The ISM now begins to write the word or byte.
VPP must be held at VPPH until the write is completed
(SR7 = 1).
While the ISM executes the WRITE, the ISM status
bit (SR7) is at “0,” and the device does not respond to
any commands. Any READ operation produces the
status register contents on DQ0–DQ7. When the ISM
status bit (SR7) is set to a logic 1, the WRITE has been
completed, and the device enters status register read
mode until another command is given.
After the ISM has initiated the WRITE, it cannot be
aborted except by a RESET or by powering down the
part. Doing either during a WRITE corrupts the data
being written. If only the WRITE SETUP command has
been given, the WRITE may be nullified by performing
a null WRITE. To execute a null WRITE, FFh must be
written when BYTE# is LOW, or FFFFh must be written
when BYTE# is HIGH. When the ISM status bit (SR7)
has been set, the device is in the status register read
mode until another command is issued.
Table 3: Command Sequences
COMMANDS
BUS
FIRST CYCLE
SECOND CYCLE
CYCLES
REQ’D OPERATION ADDRESS DATA OPERATION ADDRESS DATA NOTES
READ ARRAY
1
WRITE
IDENTIFY DEVICE
3
WRITE
READ STATUS REGISTER
2
WRITE
CLEAR STATUS REGISTER
1
WRITE
ERASE SETUP/CONFIRM
2
WRITE
ERASE SUSPEND/RESUME
2
WRITE
WRITE SETUP/WRITE
2
WRITE
ALTERNATE WORD/BYTE
WRITE
2
WRITE
X
FFh
1
X
90h
READ
IA
ID
2, 3
X
70h
READ
X
SRD
4
X
50h
X
20h
WRITE
BA
D0h 5, 6
X
B0h
WRITE
X
D0h
X
40h
WRITE
WA
WD 6, 7
X
10h
WRITE
WA
WD 6, 7
Notes: 1. Must follow WRITE or ERASE CONFIRM commands to the CEL to enable Flash array READ cycles.
2. IA = Identify Address: 00h for manufacturer compatibility ID; 01h for device ID.
3. ID = Identify Data.
4. SRD = Status Register Data.
5. BA = Block Address (A12–A19).
6. Addresses are “Don’t Care” in first cycle but must be held stable.
7. WA = Address to be written; WD = Data to be written to WA.
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
12Micron Technology, Inc. Reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
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