MT28F008B5VG-8T View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT28F008B5VG-8T' PDF : 30 Pages View PDF
8Mb
SMART 5 BOOT BLOCK FLASH MEMORY
WRITE/ERASE CYCLE ENDURANCE
The MT28F800B5 and MT28F008B5 are designed
and fabricated to meet advanced firmware storage
requirements. To ensure this level of reliability, VPP
must be at 5V ±10% during WRITE or ERASE cycles.
Due to process technology advances, 5V VPP is optimal
for application and production programming.
POWER USAGE
The MT28F800B5 and MT28F008B5 offer several
power-saving features that may be utilized in the array
read mode to conserve power. Deep power-down
mode is enabled by bringing RP# LOW. Current draw
(ICC) in this mode is a maximum of 20µA. When CE# is
HIGH, the device enters standby mode. In this mode,
maximum ICC current is 130µA. If CE# is brought HIGH
during a WRITE or ERASE, the ISM continues to oper-
ate, and the device consumes the respective active
power until the write or erase is completed.
POWER-UP
The likelihood of unwanted WRITE or ERASE, oper-
ations is minimized because two consecutive cycles
are required to execute either operation. However, to
reset the ISM and to provide additional protection
while VCC is ramping, one of the following conditions
must be met:
• RP# must be held LOW until VCC is at valid func-
tional level; or
• CE# or WE# may be held HIGH and RP# must be
toggled from VCC-GND-VCC.
After a power-up or RESET, the status register is
reset, and the device enters the array read mode.
Figure 2:
Power-Up/Reset Timing Diagram
RP#
VCC
(5V)
Note 1
tAA
Address
VALID
Data
VALID
tRWH
UNDEFINED
NOTE: 1. VCC must be within the valid operating range before RP#
goes HIGH.
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
14Micron Technology, Inc. Reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
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