MT28F008B5VG-8T View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT28F008B5VG-8T' PDF : 30 Pages View PDF
8Mb
SMART 5 BOOT BLOCK FLASH MEMORY
SELF-TIMED WRITE SEQUENCE
(WORD OR BYTE WRITE)1
COMPLETE WRITE
STATUS-CHECK SEQUENCE
Start
Start (WRITE completed)
WRITE 40h or 10h
VPP = 5V
WRITE Word or Byte
Address/Data
SR3 = 0?
YES
NO VPP Error4, 5
SR4 = 0?
YES
NO BYTE/WORD WRITE Error5
WRITE Successful
STATUS REGISTER
READ
SR7 = 1?
NO
YES
Complete Status2
Check (optional)
WRITE Complete 3
Notes: 1. Sequence may be repeated for additional BYTE or WORD WRITEs.
2. Complete status check is not required. However, if SR3 = 1, further WRITEs are inhibited until the status register
is cleared.
3. Device will be in status register read mode. To return to the array read mode, the FFh command must be issued.
4. If SR3 is set during a WRITE or BLOCK ERASE attempt, CLEAR STATUS REGISTER must be issued before further
WRITE or ERASE operations are allowed by the CEL.
5. Status register bits 3-5 must be cleared using CLEAR STATUS REGISTER.
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
15Micron Technology, Inc. Reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
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