MT28F008B5VG-8T View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT28F008B5VG-8T' PDF : 30 Pages View PDF
8Mb
SMART 5 BOOT BLOCK FLASH MEMORY
SELF-TIMED BLOCK ERASE SEQUENCE1
Start
COMPLETE BLOCK ERASE
STATUS-CHECK SEQUENCE
Start (ERASE completed)
WRITE 20h
VPP = 5V
WRITE D0h,
Block Address
STATUS REGISTER
READ
NO
SR7 = 1?
NO
Suspend ERASE?
SR3 = 0?
NO
YES
SR4, 5 = 1?
YES
NO
SR5 = 0?
NO
VPP Error5, 6
Command Sequence Error6
BLOCK ERASE Error6
YES
ERASE Successful
YES
Complete Status2
Check (optional)
ERASE Complete 3
YES
Suspend 4
Sequence
ERASE Resumed
Notes: 1. Sequence may be repeated to erase additional blocks.
2. Complete status check is not required. However, if SR3 = 1, further ERASEs are inhibited until the status register
is cleared.
3. To return to the array read mode, the FFh command must be issued.
4. Refer to the ERASE SUSPEND flowchart for more information.
5. If SR3 is set during a WRITE or BLOCK ERASE attempt, CLEAR STATUS REGISTER must be issued before further
WRITE or ERASE operations are allowed by the CEL.
6. Status register bits 3-5 must be cleared using CLEAR STATUS REGISTER.
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
16Micron Technology, Inc. Reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
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