128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
AC CHARACTERISTICS – READ-ONLY OPERATIONS
(Notes: 1, 2, 4); Commercial Temperature (0ºC ≤ TA ≤ +85ºC), Extended Temperature (-40ºC ≤ TA ≤ +85ºC)
PARAMETER
READ/WRITE Cycle Time
Address to Output Delay
CEx to Output Delay
OE# to Non-Array Output Delay
OE# to Array Output Delay
RP# HIGH to Output Delay
CEx to Output in Low-Z
OE# to Output in Low-Z
CEx HIGH to Output in High-Z
OE# HIGH to Output in High-Z
Output Hold from Address, CEx, or OE#
Change, Whichever Occurs First
CEx LOW to BYTE# HIGH or LOW
BYTE# to Output Delay
BYTE# to Output in High-Z
CEx HIGH to CEx LOW
Page Address Access Time
SYMBOL
tRC
tAA
tACE
tAOE
tAOA
tRWH
tOEC
tOEO
tODC
tODO
tOH
DENSITY
32Mb
64Mb
128Mb
32Mb
64Mb
128Mb
32Mb
64Mb
128Mb
ALL
ALL
32Mb
64Mb
128Mb
ALL
ALL
ALL
ALL
ALL
VCC = 2.7V–3.6V
VCCQ = 2.7V–3.6V
or 4.5V–5.5V
MIN
MAX
110
120
150
110
120
150
110
120
150
50
25
150
180
210
0
0
35
15
0
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCB
ALL
tABY
ALL
tODB
ALL
tCWH
ALL
tAPA
ALL
10
ns
1,000
ns
1,000
ns
0
ns
25
ns
NOTES
3, 5
5
6
6
6
6
6
6
6
6
6
NOTE:
1. CEx LOW is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEx HIGH is defined at the first edge
of CE0, CE1, or CE2 that disables the device (see Table 2).
2. See AC Input/Output Reference Waveforms for the maximum allowable input slew rate.
3. OE# may be delayed up to tACE - tAOE after the first edge of CEx that enables the device (see Table 2) without impact
on tACE .
4. See Figures 12 and 13, Transient Input/Output Reference Waveform for VCCQ = 2.7V–3.6V or VCCQ = 4.5V–5.5V, and
Transient Equivalent Testing Load Circuit for testing characteristics.
5. When reading the Flash array, a faster tAOE applies. Nonarray READs refer to status register READs, QUERY READs, or
DEVICE IDENTIFIER READs.
6. Sampled, not 100% tested.
128Mb, 64Mb, 32Mb Q-Flash Memory
MT28F640J3_7.p65 – Rev. 6, Pub. 8/02
43
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.