MT46V2M32 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT46V2M32' PDF : 65 Pages View PDF
CAPACITANCE
(Note: 13; notes appear on pages 47–50)
PARAMETER
Delta Input/Output Capacitance: DQs, DQS, DM
Delta Input Capacitance: Command and Address
Delta Input Capacitance: CK, CK#
Input/Output Capacitance: DQs, DQS, DM
Input Capacitance: Command and Address
Input Capacitance: CK, CK#
Input Capacitance: CKE
64Mb: x32
DDR SDRAM
SYMBOL MIN
DCIO
–
DCI1
–
DCI2
–
CIO
4.0
CI1
2.0
CI2
2.0
CI3
2.0
MAX
0.50
0.50
0.25
5.0
3.0
3.5
3.5
UNITS
pF
pF
pF
pF
pF
pF
pF
NOTES
29
29
29
IDD SPECIFICATIONS AND CONDITIONS
(Notes: 1-5, 10, 12, 14; notes appear on pages 47–50) (0°C ≤ TA ≤ +70°C; VDDQ = 2.5V/+2.65V, VDD=2.5V/+2.65V)
MAX
PARAMETER/CONDITION
SYMBOL -5
Operating Current: One bank; Active-Precharge; tRC = tRC MIN; IDD0 180
tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice
per clock cyle; Address and control inputs changing once
per clock cycle
-55 -6
175 165
-65 UNITS NOTES
155 mA 22
Operating Current: One bank; Active-Read-Precharge;
Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA;
Address and control inputs changing once per clock cycle
IDD1 200 195 190 185 mA 22
Precharge Power-Down Standby Current: All banks idle;
Power-down mode; tCK = tCK (MIN); CKE = LOW
IDD2P
3
33
3 mA 32
Idle Standby Current: CS# = HIGH; All banks idle;
tCK = tCK (MIN); CKE = HIGH; Address and other control inputs
changing once per clock cycle
IDD2N 120 110 100 90 mA
Active Power-Down Standby Current: One bank active;
Power-down mode; tCK = tCK (MIN); CKE = LOW
IDD3P 70 65 60 55 mA 32
Active Standby Current: CS# = HIGH; CKE = HIGH;
IDD3N 125 113 105 95 mA 22
One bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN);
DQ, DM, and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per clock cycle
Operating Current: Burst = 2; Reads; Continuous burst;
One bank active; Address and control inputs changing once per
clock cycle; tCK = tCK (MIN); IOUT = 0mA
IDD4R 355 330 310 295 mA
Operating Current: Burst = 2; Writes; Continuous burst;
One bank active; Address and control inputs changing once per
clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs
changing twice per clock cycle
IDD4W 270 250 240 220 mA
Auto Refresh Current
tRC = tRFC (MIN) IDD5 245 245 245 245 mA 22
tRC = 7.8µs
IDD6 3.5 3.5 3.5 3.5 mA 27
Self Refresh Current: CKE ≤ 0.2V
Standard
IDD7
2
22
2 mA 11
64Mb: x32 DDR SDRAM
2M32DDR-07.p65 – Rev. 12/01
44
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
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