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MT46V2M32 View Datasheet(PDF) - Micron Technology

Part Name
Description
MFG CO.
MT46V2M32
Micron
Micron Technology Micron
'MT46V2M32' PDF : 65 Pages View PDF
64Mb: x32
DDR SDRAM
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 1-5, 14-17, 33; notes appear on pages 4750 ) (0°C TA +70°C; VDDQ = +2.65V, VDD = +2.65V)
AC CHARACTERISTICS
-6
-65
PARAMETER
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time
Address and control input setup time
Address and control input pulse width
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
REFRESH to REFRESH command interval
Average periodic refresh interval
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS Read preamble
DQS Read postamble
ACTIVE bank a to ACTIVE bank b command
Terminating voltage delay to VDD
DQS Write preamble
DQS Write preamble setup time
DQS Write postamble
Write recovery time
Internal WRITE to READ command delay
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
Data valid output window
CL = 3
CL = 2
SYMBOL
tAC
tCH
tCL
tCK (3)
tCK (2)
tDH
tDS
tDIPW
tDQSCK
tDQSH
tDQSL
tDQSQ
tDQSS
tDSS
tDSH
tHP
tHZ
tLZ
tIH
tIS
tIPW
tMRD
tQH
tRAS
tRAP
tRC
tRFC
tREFC
tREFI
tRCD
tRP
tRPRE
tRPST
tRRD
tVTD
tWPRE
tWPRES
tWPST
tWR
tWTR
tXSNR
tXSRD
na
MIN MAX MIN MAX
-0.75 +0.75 -0.75 +0.75
0.45 0.55 0.45 0.55
0.45 0.55 0.45 0.55
6
12
6.5
12
10
12
10
12
0.6
0.6
0.6
0.6
1.5
1.5
-0.75 +0.75 -0.75 +0.75
0.4
0.4
0.4
0.4
0.5
0.5
0.75 1.25 0.75 1.25
0.25
0.25
0.2
tCH,tCL
0.2
tCH,tCL
-0.6
-0.65
-0.6
-0.65
1
1
1
1
2
2
2
2
tHP
tHP
-0.65ns
-0.7ns
40 120K 40 120K
tRAS(MIN) - (burst length * tCK/2)
58
59.5
66
66
7.8
18
18
0.9
1.1
0.4
0.6
2
0
0.25
0
0
0.4
0.6
2
1
66
200
tQH-tDQSQ
7.8
19.5
19.5
0.9
1.1
0.4
0.6
2
0
0.25
0
0
0.4
0.6
2
1
66
200
tQH-tDQSQ
UNITS
ns
tCK
tCK
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
tCK
ns
ns
ns
ns
ns
µs
µs
ns
ns
tCK
tCK
tCK
ns
tCK
ns
tCK
tCK
tCK
ns
tCK
ns
NOTES
30
30
41
26, 31
26, 31
31
25, 26
34
18
18
14
14
25, 26
34
35
45
40
23
23
20, 21
19
25
64Mb: x32 DDR SDRAM
2M32DDR-07.p65 Rev. 12/01
46
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
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