MT46V2M32 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT46V2M32' PDF : 65 Pages View PDF
64Mb: x32
DDR SDRAM
NOTES (continued)
37. Reduced Output Drive Curves:
a) The full variation in driver pull-down current
from minimum to maximum process, tempera-
ture and voltage will lie within the outer
bounding lines of the V-I curve of Figures E and F.
b)The variation in driver pull-down current
within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figures E and F.
c) The full variation in driver pull-up current from
minimum to maximum process, temperature
and voltage will lie within the outer bounding
lines of the V-I curve of Figures G and H.
d)The variation in driver pull-up current within
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within
the inner bounding lines of the V-I curve of
Figures G and H.
80
70
60
50
40
30
20
10
0
0.0
50
40
30
20
10
Figure E
Pull-Down Characteristics
Maximum
Nominal high
Nominal low
Minimum
0.5
1.0
1.5
VOUT (V)
Figure F
Pull-Down Characteristics
2.0
2.5
Maximum
Nominal high
Nominal low
Minimum
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
VOUT (V)
e) The full variation in the ratio of the maximum
to minimum pull-up and pull-down current
will not exceed 1.7, for device drain-to-source
voltages from 0 to VDDQ/2.
f) The full variation in the ratio of the nominal
pull-up to pull-down current should be unity
±10%, for device drain-to-source voltages from
0 to 0.1V to 1.0V.
38. The voltage levels used are derived from the
referenced test load. In practice, the voltage
levels obtained from a properly terminated bus
will provide significantly different voltage values.
39. VIH overshoot: VIH (MAX) = VDDQ+1.5V for a pulse
width ≤ 3ns and the pulse width can not be
greater than 1/3 of the cycle rate. VIL undershoot:
VIL (MIN) = -1.5V for a pulse width ≤ 3ns and the
pulse width can not be greater than 1/3 of the
cycle rate.
40. CKE must be active (high) during the entire time
a refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge,
until tREF later.
41. Whenever the operating frequency is altered, not
including jitter, the DLL is required to be reset
and followed by a 200 clock cycle delay.
42. VDD and VDDQ must track each other.
43. Will slightly adjust with VDD/VDDQ level.
44. During initialization, VDDQ, VTT, and VREF must be
equal to or less than VDD + 0.3V. Alternatively, VTT
may be 1.35V maximum during power up, even if
VDD/VDDQ are 0 volts, provided a minimum of 42
ohms or series resistance is used between the VTT
supply and the input pin.
45. tRCD ≤ tRAP
0
-20
-40
-60
-80
-100
-120
0.0
Figure G
Pull-Up Characteristics
Minimum
Nominal low
Nominal high
Maximum
0.5
1.0
1.5
2.0
2.5
VDDQ - VOUT (V)
64Mb: x32 DDR SDRAM
2M32DDR-07.p65 – Rev. 12/01
50
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
Share Link: 
