MT46V4M32 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT46V4M32' PDF : 66 Pages View PDF
CK#
CK
COMMAND
T0
WRITE
ADDRESS
Bank a,
Col b
tDQSS (NOM)
DQS
tDQSS
DQ
DM
Figure 20
WRITE to READ – Interrupting
T1 T1n T2 T2n T3
T4
NOP
NOP
READ
NOP
tWTR
Bank a,
Col n
CL = 2
DI
b
tDQSS (MIN)
DQS
DQ
DM
tDQSS
DI
b
CL = 2
tDQSS (MAX)
DQS
tDQSS
DQ
DI
b
DM
CL = 2
ADVANCE
128Mb: x32
DDR SDRAM
T5 T5n T6 T6n
NOP
NOP
DI
n
DI
n
DI
n
DON T CARE
TRANSITIONING DATA
NOTE: 1. DI b = data-in for column b.
2. An interrupted burst of 4 or 8 is shown; two data elements are written.
3. One subsequent element of data-in is applied in the programmed order following DI b.
4. tWTR is referenced from the first positive CK edge after the last data-in pair.
5. A8 is LOW with the WRITE command (auto precharge is disabled).
6. DQS is required at T2 and T2n (nominal case) to register DM.
7. If the burst of 8 was used, DM would not be required at T3-T4n because the READ command would
mask the last two data elements.
128Mb: x32 DDR SDRAM
4M32DDR_B.p65 – Rev. B, Pub. 7/02
30
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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