MT48H8M32LFBF-8 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48H8M32LFBF-8' PDF : 71 Pages View PDF
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
Truth Tables
5. The following states must not be interrupted by any executable command; DESELECT or
NOP commands must be applied on each positive clock edge during these states.
Refreshing:
Accessing MR:
Precharging all:
Starts with registration of an AUTO REFRESH command and ends
when tRFC is met. Once tRFC is met, the Mobile SDRAM will be in the
all banks idle state.
Starts with registration of an LMR command and ends when tMRD
has been met. Once tMRD is met, the Mobile SDRAM will be in the
all banks idle state.
Starts with registration of a PRECHARGE ALL command and ends
when tRP is met. Once tRP is met, all banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid
state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regard-
less of bank.
10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with
auto precharge enabled and READs or WRITEs with auto precharge disabled.
11. Does not affect the state of the bank and acts as a NOP to that bank.
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
MT48H16M16LF_2.fm - Rev F 4/07 EN
42
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