MT48H8M32LFBF-8 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48H8M32LFBF-8' PDF : 71 Pages View PDF
Notes
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
Notes
1. All voltages referenced to VSS.
2. This parameter is sampled. VDD, VDDQ = +1.8V; TA = 25°C; ball under test biased at
0.9V; f = 1 MHz.
3. IDD is dependent on output loading and cycle rates. Specified values are obtained
with minimum cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle time at which proper
operation over the full temperature range (–40°C ≤ TA ≤ +85°C for TA on IT parts) is
ensured.
6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH
commands, before proper device operation is ensured. (VDD and VDDQ must be pow-
ered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO
REFRESH command wake-ups should be repeated any time the tREF refresh require-
ment is exceeded.
7. AC characteristics assume tT = 1ns.
8. In addition to meeting the transition rate specification, the clock and CKE must tran-
sit between VIH and VIL (or between VIL and VIH) in a monotonic manner.
9. Outputs measured for 1.8V at 0.9V with equivalent load:
Q
20pF
Test loads with full DQ driver strength. Performance will vary with actual system DQ
bus capacitive loading, termination, and programmed drive strength.
10. tHZ defines the time at which the output achieves the open circuit condition; it is not
a reference to VOH or VOL. The last valid data element will meet tOH before going
High-Z.
11. AC timing and IDD tests have VIL and VIH, with timing referenced to VIH/2 = crossover
point. If the input transition time is longer than tT (MAX), then the timing is refer-
enced at VIL (MAX) and VIH (MIN) and no longer at the VIH/2 crossover point.
12. Other input signals are allowed to transition no more than once every two clocks and
are otherwise at valid VIH or VIL levels.
13. IDD specifications are tested after the device is properly initialized.
14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum
cycle rate.
15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at
minimum cycle rate.
16. Timing actually specified by tWR.
17. Required clocks are specified by JEDEC functionality and are not dependent on any
timing parameter.
18. The IDD current will increase or decrease proportionally according to the amount of
frequency alteration for the test condition.
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. Based on tCK = 7.5ns for -75,tCK = 8ns for -8, at CL = 3.
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
MT48H16M16LF_2.fm - Rev F 4/07 EN
51
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
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