MT48H8M32LFBF-8 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48H8M32LFBF-8' PDF : 71 Pages View PDF
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
Notes
22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width ≤ 3ns, and the pulse width
cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = –2V for
a pulse width ≤ 3ns.
23. The clock frequency can only be changed during clock stop, power-down, or while in
a self-refresh mode.
24. Auto precharge mode only. The precharge timing budget (tRP) begins at 7ns for -8
after the first clock delay, after the last WRITE is executed. May not exceed limit set for
precharge mode.The clock frequency can only be changed during
25. Parameter guaranteed by design.
26. CKE is HIGH during refresh command period tRFC (MIN) else CKE is LOW.
27. The IDD6 limit is actually a nominal value and does not result in a fail value.
28. Values for IDD7 for 70°C, 45°C, 15°C, and IDD7 1/2-bank and 1/4-bank are sampled
only. Values for IDD7 4-bank, 2-bank, and 1-bank for 85°C are 100 percent tested.
29. Deep power-down current is a nominal value at 25°C. This parameter is not tested.
30. Test conditions include 500ms delay prior to measurement.
31. Auto precharge mode only. The precharge timing budget (tRP) begins at 7.5ns for -75
and 7ns for -8 after the first clock delay, after the last WRITE is executed. For auto pre-
charge mode, at least one clock cycle is required during tWR.
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
MT48H16M16LF_2.fm - Rev F 4/07 EN
52
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
Share Link: 
