MT48H8M32LFBF-8 View Datasheet(PDF) - Micron Technology
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MFG CO.
'MT48H8M32LFBF-8' PDF : 71 Pages View PDF
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Timing Diagrams
Timing Diagrams
Figure 34: Initialize and Load Mode Register
((
CLK
))
((
))
((
))
CKE
((
))
((
COMMAND1
))
((
))
((
))
DQM
((
))
T0
tCK
tCKS tCKH
tCMS tCMH
NOP
ADDR
A10
BA0, BA1
DQ
((
))
((
))
((
))
((
))
((
))
((
))
((
))
T = 100µs
High-Z
Power-up:
VDD and
CLK stable
T1
Tn + 1
To + 1
Tp + 1
Tq + 1
Tr + 1
((
((
((
((
((
((
))
))
))
))
))
))
((
((
((
((
((
((
))
))
))
))
))
))
((
))
((
))
((
))
PRE
((
))
((
))
((
))
((
))
((
))
ALL BANKS ( (
))
((
))
tAS tAH
((
))
((
))
((
))
tRP
Precharge
all banks
((
))
((
))
((
))
AR
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
((
((
((
))
))
))
))
((
((
((
((
))
))
))
))
((
((
((
((
))
))
))
))
AR
((
LMR
((
LMR
((
VALID ( (
))
))
))
))
((
((
))
))
((
((
))
))
tAS tAH
((
((
))
))
((
CODE
((
))
))
((
))
((
))
((
))
CODE
((
))
((
))
((
))
((
))
VALID
((
))
((
((
))
))
((
CODE
((
))
))
tAS tAH
((
((
) ) BA0 = L, ) )
((
BA1 = L ( (
))
))
((
))
CODE
((
))
((
BBAA00==LL,, ) )
BBAA11==HL ( (
))
((
))
VALID
((
))
((
))
VALID
((
))
((
((
((
((
((
))
))
))
))
))
tRFC2
tRFC2
tMRD3
tMRD3
Load Mode Load Extended
Register Mode Register
DON’T CARE
Notes:
1. PRE = PRECHARGE command; AR = AUTO REFRESH command; LMR = LOAD MODE REGISTER
command.
2. Only NOPs or COMMAND INHIBITs may be issued during tRFC time.
3. At least one NOP or COMMAND INHIBIT is required during tMRD time.
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
MT48H16M16LF_2.fm - Rev F 4/07 EN
53
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