MT48H8M32LFBF-8 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48H8M32LFBF-8' PDF : 71 Pages View PDF
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
Timing Diagrams
Figure 41: Single READ – without Auto Precharge
T0
CLK
T1
T2
T3
tCK
tCL
tCH
tCKS tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
DQM
ADDR
tAS tAH
ROW
NOP
READ
tCMS tCMH
NOP2
COLUMN m
A10
BA0, BA1
tAS tAH
ROW
tAS tAH
BANK
DISABLE AUTO PRECHARGE
BANK
tAC
DQ
tRCD
tRAS
tRC
tLZ
CL
T4
T5
NOP2
PRECHARGE
ALL BANKS
SINGLE BANK
tOH
DOUT m
tHZ
BANK(S)
T6
NOP
tRP
T7
ACTIVE
ROW
ROW
BANK
T8
NOP
DON’T CARE
UNDEFINED
Notes:
1. For this example, BL = 4, CL = 2, and the READ burst is followed by a manual PRECHARGE.
2. PRECHARGE command not allowed or tRAS would be violated.
See Table 11 on page 46.
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
MT48H16M16LF_2.fm - Rev F 4/07 EN
60
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