MT48H8M32LFBF-8 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48H8M32LFBF-8' PDF : 71 Pages View PDF
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM
Timing Diagrams
Figure 35: Power-Down Mode
T0
T1
T2
CLK
tCK
tCL
((
))
tCH
((
))
tCKS
CKE
((
tCKS tCKH
))
tCMS tCMH
((
COMMAND PRECHARGE
NOP
NOP
))
((
))
Tn + 1
tCKS
Tn + 2
NOP
ACTIVE
((
DQM
))
((
))
ADDR
A10
ALL BANKS
SINGLE BANK
tAS tAH
BA0, BA1
BANK(S)
High-Z
DQ
Two clock cycles
Precharge all
active banks
All banks idle, enter
power-down mode
((
))
((
))
((
))
((
))
((
))
((
))
((
))
Input buffers gated off while in
power-down mode
Exit power-down mode
ROW
ROW
BANK
All banks idle
DON’T CARE
Notes: 1. Violating refresh requirements during power-down may result in a loss of data.
See Table 11 on page 46.
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
MT48H16M16LF_2.fm - Rev F 4/07 EN
54
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
Share Link: 
