MT48LC16M4A2TG View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC16M4A2TG' PDF : 55 Pages View PDF
64Mb: x4, x8, x16
SDRAM
INITIALIZE AND LOAD MODE REGISTER 1
CLK
CKE
COMMAND
T0
((
))
tCKS tCKH
T1
tCK
Tn + 1
((
))
((
tCH
))
((
((
))
))
((
((
))
))
tCMS tCMH tCMS tCMH tCMS tCMH
((
))
((
NOP
))
((
))
PRECHARGE ( (
))
AUTO
REFRESH
((
))
((
))
((
))
((
))
NOP( ( NOP
))
((
DQM /
))
DQML, DQMH
((
))
((
((
))
))
((
((
))
))
((
A0-A9, A11 ) )
((
))
((
))
((
))
((
A10
))
((
))
ALL BANKS ( (
))
((
SINGLE BANK ) )
BA0, BA1
DQ
((
))
((
))
((
))
T = 100µs
MIN
High-Z
((
ALL
))
BANKS
((
))
((
))
tRP
((
))
((
))
((
))
((
))
((
))
((
))
tRFC
Power-up:
VDD and
CLK stable
Precharge
all banks
AUTO REFRESH
To + 1
tCL
((
))
((
))
((
))
AUTO
REFRESH
((
))
NOP( ( NOP
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
tRFC
AUTO REFRESH
Tp + 1
Tp + 2
Tp + 3
LOAD MODE
REGISTER
NOP
ACTIVE
tAS tAH
CODE
tAS tAH
CODE
ROW
ROW
BANK
tMRD
Program Mode Register 2, 3, 4
DON’T CARE
TIMING PARAMETERS
SYMBOL*
tAH
tAS
tCH
tCL
tCK(3)
tCK(2)
tCKH
-6
-7E
-75
-8E
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
1
0.8
0.8
1
ns
1.5
1.5
1.5
2
ns
2.5
2.5
2.5
3
ns
2.5
2.5
2.5
3
ns
6
7
7.5
8
ns
–
7.5
10
10
ns
1
0.8
0.8
1
ns
SYMBOL*
tCKS
tCMH
tCMS
tMRD3
tRFC
tRP
-6
-7E
-75
-8E
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
1.5
1.5
1.5
2
ns
1
0.8
0.8
1
ns
1.5
1.5
1.5
2
ns
2
2
2
2
tCK
60
66
66
70
ns
18
15
20
20
ns
*CAS latency indicated in parentheses.
NOTE:
1. If CS# is HIGH at clock HIGH time, all commands applied are NOP.
2. The mode register may be loaded prior to the AUTO REFRESH cycles if desired.
3. JEDEC and PC100 specify three clocks.
4. Outputs are guaranteed High-Z after command is issued.
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
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