MT48LC16M4A2TG View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'MT48LC16M4A2TG' PDF : 55 Pages View PDF
64Mb: x4, x8, x16
SDRAM
T0
CLK
tCK
CKE
tCKS tCKH
tCMS tCMH
COMMAND PRECHARGE
DQM/
DQML, DQMH
A0-A9, A11
A10
BA0, BA1
ALL BANKS
SINGLE BANK
tAS tAH
BANK(S)
High-Z
DQ
Precharge all
active banks
T1
tCH
SELF REFRESH MODE
T2
tCL
tCKS
((
))
((
))
≥ tRAS(MIN)1
((
))
Tn + 1
( ( To + 1
))
((
))
((
))
((
))
NOP
((
AUTO
))
REFRESH ( (
))
((
))
((
))
((
))
((
))
((
))
((
))
((
NOP
))
((
or
COMMAND
INHIBIT
))
((
))
((
))
((
))
((
))
((
))
((
))
((
((
))
))
((
((
))
))
((
((
))
))
tRP
tXSR2
Enter self refresh mode
Exit self refresh mode
(Restart refresh time base)
CLK stable prior to exiting
self refresh mode
To + 2
AUTO
REFRESH
DON’T CARE
TIMING PARAMETERS
-6
SYMBOL*
tAH
tAS
tCH
tCL
tCK(3)
tCK(2)
tCKH
MIN
1
1.5
2.5
2.5
6
–
1
MAX
-7E
MIN MAX
0.8
1.5
2.5
2.5
7
7.5
0.8
-75
MIN MAX
0.8
1.5
2.5
2.5
7.5
10
0.8
-8E
MIN MAX UNITS
1
ns
2
ns
3
ns
3
ns
8
ns
10
ns
1
ns
*CAS latency indicated in parentheses.
-6
-7E
-75
-8E
SYMBOL* MIN MAX MIN MAX MIN MAX MIN MAX UNITS
tCKS
1.5
1.5
1.5
2
ns
tCMH
1
0.8
0.8
1
ns
tCMS
1.5
1.5
1.5
2
ns
tRAS
42 120,000 37 120,000 44 120,000 50 120,000 ns
tRP
18
15
20
20
ns
tXSR
70
67
75
80
ns
NOTES: 1. No maximum time limit for Self Refresh mode. tRAS(MAX) applies to non-Self Refresh mode.
2. tXSR requires minimum of two clocks regardless of frequency and timing.
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
40
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
Share Link: 
