NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
DLL on/off switching procedure
DDR3/L DLL-off mode is entered by setting MR1 bit A0 to “1”; this will disable the DLL for subsequent operation until A0 bit
set back to “0”.
DLL “on” to DLL “off” Procedure
To switch from DLL “on” to DLL “off” requires the frequency to be changed during Self-Refresh outlined in the following
procedure:
1. Starting from Idle state (all banks pre-charged, all timing fulfilled, and DRAMs On-die Termination resistors, RTT,
must be in high impedance state before MRS to MR1 to disable the DLL).
2. Set MR1 Bit A0 to “1” to disable the DLL.
3. Wait tMOD.
4. Enter Self Refresh Mode; wait until (tCKSRE) satisfied.
5. Change frequency, in guidance with “Input Clock Frequency Change” section.
6. Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs.
7. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until all tMOD timings from
any MRS command are satisfied. In addition, if any ODT features were enabled in the mode registers when Self
Refresh mode was entered, the ODT signal must continuously be registered LOW until all tMOD timings from any
MRS command are satisfied. If both ODT features were disabled in the mode registers when Self Refresh mode was
entered, ODT signal can be registered LOW or HIGH.
8. Wait tXS, and then set Mode Registers with appropriate values (especially an update of CL, CWL, and WR may be
necessary. A ZQCL command may also be issued after tXS).
9. Wait for tMOD, and then DRAM is ready for next command.
Fig. 14: DLL Switch Sequence from DLL-on to DLL-off
CK
CK
CMD
1)
T0
MRS 2)
CKE
T1
tMOD
NOP
Ta0
Ta1
Tb0
Tc0
Td0
SRE 3)
tCKSRE
NOP
4)
tCKESR
tCKSRX 5)
SRX 6)
Td1
Te 0
Te1
Tf0
tXS
NOP
MRS 7 )
tMOD
NOP
Valid 8)
Valid 8)
ODT
Time
break
Do not
Care
Note:
ODT: Static LOW in case RTT_Nom and RTT_WR is enabled, otherwise static Low or High
1) Starting with Idle State, RTT in Hi-Z State.
2) Disable DLL by setting MR1 Bit A0 to 1.
3) Enter SR.
4) Change Frequency.
5) Clock must be stable at least tCKSRX.
6) Exit SR.
7) Update Mode registers with DLL off parameters setting.
8) Any valid command.
Valid 8)
REV 1.2
May. 2011
CONSUMER DRAM
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