NT5CC64M16DP-BE View Datasheet(PDF) - Nanya Technology
Part Name
Description
MFG CO.
'NT5CC64M16DP-BE' PDF : 138 Pages View PDF
NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
Table 17:MPR MR3 Register Definition
MR3 A[2]
MR3 A[1:0]
Function
Normal operation, no MPR transaction.
don't care
0
All subsequent Reads will come from DRAM array.
(0 or 1)
All subsequent Writes will go to DRAM array.
See the following
1
Enable MPR mode, subsequent RD/RDA commands defined by MR3 A[1:0].
table
MPR Functional Description
One bit wide logical interface via all DQ pins during READ operation.
Register Read on x8:
DQ [0] drives information from MPR.
DQ [7:1] either drive the same information as DQ [0], or they drive 0.
Addressing during for Multi Purpose Register reads for all MPR agents:
BA [2:0]: don’t care.
A [1:0]: A [1:0] must be equal to “00”. Data read burst order in nibble is fixed.
A[2]: For BL=8, A[2] must be equal to 0, burst order is fixed to [0,1,2,3,4,5,6,7]; For Burst chop 4 cases, the burst order is
switched on nibble base, A[2]=0, burst order: 0,1,2,3, A[2]=1, burst order: 4,5,6,7. *)
A [9:3]: don’t care.
A10/AP: don’t care.
A12/BC: Selects burst chop mode on-the-fly, if enabled within MR0
A11, A13: don’t care.
Regular interface functionality during register reads:
Support two Burst Ordering which are switched with A2 and A[1:0]=00.
Support of read burst chop (MRS and on-the-fly via A12/BC).
All other address bits (remaining column addresses bits including A10, all bank address bits) will be ignored by the
DDR3/L SDRAM.
Regular read latencies and AC timings apply.
DLL must be locked prior to MPR READs.
Note *): Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent.
REV 1.2
May. 2011
CONSUMER DRAM
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