NT5CC64M16DP-BE View Datasheet(PDF) - Nanya Technology
Part Name
Description
MFG CO.
'NT5CC64M16DP-BE' PDF : 138 Pages View PDF
NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
MPR Register Address Definition
The following table provide an overview of the available data location, how they are addressed by MR3 A[1:0] during a MRS
to MR3, and how their individual bits are mapped into the burst order bits during a Multi Purpose Register Read.
Table 18: MPR MR3 Register Definition
MR3 A[2]
MR3 A[1:0]
Function
Burst
Length
Read
Address
A[2:0]
Burst Order and Data Pattern
Burst order 0,1,2,3,4,5,6,7
Read
BL8
000
Pre-defined Data Pattern [0,1,0,1,0,1,0,1]
Predefined
Burst order 0,1,2,3
1
00
Pattern for
BC4
000
Pre-defined Data Pattern [0,1,0,1]
System
Calibration
BC4
Burst order 4,5,6,7
100
Pre-defined Data Pattern [0,1,0,1]
BL8
000
Burst order 0,1,2,3,4,5,6,7
1
01
RFU
BC4
000
Burst order 0,1,2,3
BC4
100
Burst order 4,5,6,7
BL8
000
Burst order 0,1,2,3,4,5,6,7
1
10
RFU
BC4
000
Burst order 0,1,2,3
BC4
100
Burst order 4,5,6,7
BL8
000
Burst order 0,1,2,3,4,5,6,7
1
11
RFU
BC4
000
Burst order 0,1,2,3
BC4
100
Burst order 4,5,6,7
Note: Burst order bit 0 is assigned to LSB and the burst order bit 7 is assigned to MSB of the selected MPR agent.
ACTIVE Command
The ACTIVE command is used to open (or activate) a row in a particular bank for subsequent access. The value on the
BA0-BA2 inputs selects the bank, and the addresses provided on inputs A0-A13 selects the row. These rows remain active
(or open) for accesses until a precharge command is issued to that bank. A PRECHARGE command must be issued before
opening a different row in the same bank.
REV 1.2
May. 2011
CONSUMER DRAM
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All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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