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NT5CC64M16DP-BE View Datasheet(PDF) - Nanya Technology

Part Name
Description
MFG CO.
NT5CC64M16DP-BE
Nanya
Nanya Technology Nanya
'NT5CC64M16DP-BE' PDF : 138 Pages View PDF
NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
Read Timing; Clock to Data Strobe relationship
Clock to Data Strobe relationship is shown in the following figure and is applied when the DLL is enabled and locked.
Rising data strobe edge parameters:
tDQSCK min/max describes the allowed range for a rising data strobe edge relative to CK and .
tDQSCK is the actual position of a rising strobe edge relative to CK and .
tQSH describes the data strobe high pulse width.
Falling data strobe edge parameters:
tQSL describes the data strobe low pulse width.
Fig. 23: Clock to Data Strobe Relationship
RL Measured
to this point
CK
CK
DQS, DQS
Early Strobe
tLZ(DQS)min
tRPRE
tDQSCKmin
tLZ(DQS)max
DQS, DQS
Late Strobe
tDQSCKmax
tRPRE
tQSH tQSL
tRPST
tHZ(DQS)min
tHZ(DQS)max
tRPST
NOTES: 1. Within a burst, rising strobe edge is not necessarily fixed to be always at tDQSCK(min) or tDQSCK(max). Instead, rising strobe
edge can vary between tDQSCK(min) and tDQSCK(max).
2. The DQS, DQS# differential output high time is defined by tQSH and the DQS, DQS# differential output low time is defined by
tQSL.
3. Likewise, tLZ(DQS)min and tHZ(DQS)min are not tied to tDQSCKmin (early strobe case) and tLZ(DQS)max and tHZ(DQS)max
are not tied to tDQSCKmax (late strobe case).
4. The minimum pulse width of read preamble is defined by tRPRE(min).
5. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZDSQ(max) on the right side.
6. The minimum pulse width of read postamble is defined by tRPST(min).
7. The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side.
REV 1.2
May. 2011
CONSUMER DRAM
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