NT5CC64M16DP-BE View Datasheet(PDF) - Nanya Technology
Part Name
Description
MFG CO.
'NT5CC64M16DP-BE' PDF : 138 Pages View PDF
NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
Refresh Command
The Refresh command (REF) is used during normal operation of the DDR3/L SDRAMs. This command is not persistent, so
it must be issued each time a refresh is required. The DDR3/L SDRAM requires Refresh cycles at an average periodic
interval of tREFI. When , , and
are held Low and High at the rising edge of the clock, the chip enters a
Refresh cycle. All banks of the SDRAM must be precharged and idle for a minimum of the precharge time tRP(min) before
the Refresh Command can be applied. The refresh addressing is generated by the internal refresh controller. This makes
the address bits “Don’t Care” during a Refresh command. An internal address counter suppliers the address during the
refresh cycle. No control of the external address bus is required once this cycle has started. When the refresh cycle has
completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the Refresh Command and the
next valid command, except NOP or DES, must be greater than or equal to the minimum Refresh cycle time tRFC(min) as
shown in the following figure.
In general, a Refresh command needs to be issued to the DDR3/L SDRAM regularly every tREFI interval. To allow for
improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided.
A maximum of 8 Refresh commands can be postponed during operation of the DDR3/L SDRAM, meaning that at no point
in time more than a total of 8 Refresh commands are allowed to be postponed. In case that 8 Refresh commands are
postponed in a row, the resulting maximum interval between the surrounding Refresh commands is limited to 9 x tREFI. A
maximum of 8 additional Refresh commands can be issued in advance (“pulled in”), with each one reducing the number of
regular Refresh commands required later by one. Note that pulling in more than 8 Refresh commands in advance does not
further reduce the number of regular Refresh commands required later, so that the resulting maximum interval between two
surrounding Refresh command is limited to 9 x tREFI. Before entering Self-Refresh Mode, all postponed Refresh
commands must be executed.
Fig. 33: Self-Refresh Entry/Exit Timing
T0
CK
CK
CMD
REF
DRAM must be idle
T1
NOP
NOP
tRFC
Ta0
Ta1
REF
NOP
NOP
tRFC(min)
Tb0
Tb1
Tb2
Tb3
Tc0
Tc1
Valid
Valid
Valid
Valid
Valid
REF
Valid
tREFI (max, 9 x tREFI)
DRAM must be idle
Time Break
Fig. 34: Postponing Refresh Commands (Example)
tR E F I
9 x tR E F I
t
tR E F I
REV 1.2
May. 2011
8 R E F -C o m m a n d p o stp o n ed
CONSUMER DRAM
© NANYA TECHNOLOGY CORP.
All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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