NT5CC64M16DP-BE View Datasheet(PDF) - Nanya Technology
Part Name
Description
MFG CO.
'NT5CC64M16DP-BE' PDF : 138 Pages View PDF
NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
Fig. 35: Pulled-in Refresh Commands (Example)
tR E FI
tR E F I
9 x tREFI
t
8 R E F-C om m ands pulled-in
Self-Refresh Operation
The Self-Refresh command can be used to retain data in the DDR3/L SDRAM, even if the reset of the system is powered
down. When in the Self-Refresh mode, the DDR3/L SDRAM retains data without external clocking. The DDR3/L SDRAM
device has a built-in timer to accommodate Self-Refresh operation. The Self-Refresh Entry (SRE) Command is defined by
having , , , and held low with WE high at the rising edge of the clock.
Before issuing the Self-Refreshing-Entry command, the DDR3/L SDRAM must be idle with all bank precharge state with
tRP satisfied. Also, on-die termination must be turned off before issuing Self-Refresh-Entry command, by either registering
ODT pin low “ODTL + 0.5tCK” prior to the Self-Refresh Entry command or using MRS to MR1 command. Once the
Self-Refresh Entry command is registered, CKE must be held low to keep the device in Self-Refresh mode. During normal
operation (DLL on), MR1 (A0=0), the DLL is automatically disabled upon entering Self-Refresh and is automatically
enabled (including a DLL-RESET) upon exiting Self-Refresh.
When the DDR3/L SDRAM has entered Self-Refresh mode, all of the external control signals, except CKE and
, are
“don’t care”. For proper Self-Refresh operation, all power supply and reference pins (VDD, VDDQ, VSS, VSSQ, VRefCA,
and VRefDQ) must be at valid levels. The DRAM initiates a minimum of one Refresh command internally within tCKE
period once it enters Self-Refresh mode.
The clock is internally disabled during Self-Refresh operation to save power. The minimum time that the DDR3/L SDRAM
must remain in Self-Refresh mode is tCKE. The user may change the external clock frequency or halt the external clock
tCKSRE after Self-Refresh entry is registered; however, the clock must be restarted and stable tCKSRX before the device
can exit Self-Refresh mode.
The procedure for exiting Self-Refresh requires a sequence of events. First, the clock must be stable prior to CKE going
back HIGH. Once a Self-Refresh Exit Command (SRX, combination of CKE going high and either NOP or Deselect on
command bus) is registered, a delay of at least tXS must be satisfied before a valid command not requiring a locked DLL
can be issued to the device to allow for any internal refresh in progress. Before a command which requires a locked DLL
can be applied, a delay of at least tXSDLL and applicable ZQCAL function requirements [TBD] must be satisfied.
REV 1.2
May. 2011
CONSUMER DRAM
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All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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