NT5CC64M16DP-BE View Datasheet(PDF) - Nanya Technology
Part Name
Description
MFG CO.
'NT5CC64M16DP-BE' PDF : 138 Pages View PDF
NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
Before a command that requires a locked DLL can be applied, a delay of at least tXSDLL must be satisfied. Depending on
the system environment and the amount of time spent in Self-Refresh, ZQ calibration commands may be required to
compensate for the voltage and temperature drift as described in “ZQ Calibration Commands”. To issue ZQ calibration
commands, applicable timing requirements must be satisfied.
CKE must remain HIGH for the entire Self-Refresh exit period tXSDLL for proper operation except for Self-Refresh re-entry.
Upon exit from Self-Refresh, the DDR3/L SDRAM can be put back into Self-Refresh mode after waiting at least tXS period
and issuing one refresh command (refresh period of tRFC). NOP or deselect commands must be registered on each
positive clock edge during the Self-Refresh exit interval tXS. ODT must be turned off during tXSDLL.
The use of Self-Refresh mode instructs the possibility that an internally times refresh event can be missed when CKE is
raised for exit from Self-Refresh mode. Upon exit from Self-Refresh, the DDR3/L SDRAM requires a minimum of one extra
refresh command before it is put back into Self-Refresh mode.
Fig. 36:Self-Refresh Entry/Exit Timing
T0
CK, CK
CKE
T1
T2
Ta0
tCKSRE
tCPDED
ODT
ODTL
CMD NOP
SRE
NOP
Tb0
tCKESR
Tc0
Tc1
Td0
Te0
Tf
tCKSRX
Valid Valid
Valid
SRX NOP 1) Valid 2) Valid 3)
tRF
Enter Self Refresh
Note:
1. Only NOP or DES commands
2. Valid commands not requiring a locked DLL
3. Valid commands requiring a locked DLL
Valid
tXS
tXSDLL
Exit Self Refresh
Do Not
Care
Time
Break
Valid
REV 1.2
May. 2011
CONSUMER DRAM
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All rights reserved
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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