PCF8536AT/1 View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

MFG CO.

PCF8536AT/1

Universal LCD driver for low multiplex rates including a 6 channel PWM generator

NXP Semiconductors. 

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NXP Semiconductors

PCF8536

Universal LCD low multiplex driver with 6 channel PWM generator

• A clock signal must always be supplied to the device when the display is active.

Removing the clock may freeze the LCD in a DC state, which is not suitable for the

liquid crystal. It is recommended to disable the display first and afterwards to remove

the clock signal.

8.1.4.4 Display enable

The display enable bit (E) is used to enable and disable the display. When the display is

disabled, all LCD outputs go to VSS. This function is implemented to ensure that no

voltage can be induced on the LCD outputs as it may lead to unwanted displays of

segments.

Recommended start-up sequences are found in Section 8.2.3

Remarks:

• The state of display enable has no effect on the GPO outputs.

• Display enable is not synchronized to an LCD frame boundary. Therefore using this

function to flash a display for prolonged periods is not recommended due to the

possible build-up of DC voltages on the display.

8.1.5 Command: oscillator-control

The oscillator-control command switches between internal and external oscillator and

enables or disables the pin OSCCLK. It is also used to define what the external frequency

will be.

Table 10. Oscillator-control - oscillator control command bit description

Bit

Symbol

Value

Description

7 to 3 -

00011

fixed value

2

EFR

external clock frequency applied on pin

OSCCLK

0[1]

9.6 kHz

1

230 kHz

1

COE

clock output enable for pin OSCCLK

0[1]

clock signal not available on pin OSCCLK;

pin OSCCLK is in 3-state

1

clock signal available on pin OSCCLK

0

OSC

oscillator source

0[1]

internal oscillator running

1

external oscillator used;

pin OSCCLK becomes an input;

used in combination with EFR to determine

input frequency

[1] Default value.

The bits OSC, COE, and EFR control the source and frequency of the clock used to

generate the LCD and PWM signals (see Figure 7). Valid combinations are shown in

Table 11.

PCF8536

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 6 October 2011

© NXP B.V. 2011. All rights reserved.

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