PCF8536AT/1 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
PCF8536AT/1
NXP Semiconductors.
'PCF8536AT/1' PDF : 74 Pages View PDF
NXP Semiconductors
PCF8536
Universal LCD low multiplex driver with 6 channel PWM generator
8.1.12 Command: load-data-pointer-LCD
The load-data-pointer-LCD command defines the start address of the display RAM. The
data pointer is auto incremented after each RAM write. The size of the display RAM is
dependent on the current multiplex drive mode setting, see Table 25.
Table 25. Load-data-pointer-LCD - load data pointer command bit description
Bit
Symbol
Value
Description
7 to 6 -
10
fixed value
Multiplex drive mode 1:8
5 to 0 DP[5:0]
000000[1] to 6-bit binary value of 0 to 39
10 0111
Multiplex drive mode 1:6
5 to 0 DP[5:0]
000000[1] to 6-bit binary value of 0 to 41
10 1001
Multiplex drive mode 1:4
5 to 0 DP[5:0]
000000[1] to 6-bit binary value of 0 to 43
10 1011
[1] Default value.
Remark: Data pointer values outside of the valid range will be ignored and no RAM
content will be transferred until a valid data pointer value is set.
Filling of the display RAM is described in Section 8.9.
8.1.13 Command: load-data-pointer-PWM
The load-data-pointer-PWM command defines one of the 6 PWM addresses.
Table 26. Load-data-pointer-PWM - load data pointer command bit description
Bit
Symbol
Value
Description
7 to 3 -
0111 0
fixed value
2 to 0 PP[2:0]
000[1] to 101 3-bit binary value of 0 to 5
[1] Default value.
Remark: Data pointer values outside of the valid range will be ignored and no PWM
content will be transferred until a valid data pointer value is set.
8.1.14 Command: write-RAM-data
This command will initiate the transfer of data to the display RAM. Data will be written into
the address defined by the load-data-pointer-LCD command. RAM filling is described in
Section 8.9.
Table 27. Write-RAM-data - write RAM data command bit description[1]
Bit
Symbol
Value
Description
7 to 0 D[7:0]
00000000 to writing data byte-wise to RAM
11111111[2]
[1] For this command to be effective bit RS[1:0] of the control byte has to be set logic 01, see Table 36 on
page 46.
[2] After Power-On Reset (POR), the RAM content is random and should be brought to a defined status by
writing meaningful content otherwise unexpected display content may appear.
PCF8536
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 6 October 2011
© NXP B.V. 2011. All rights reserved.
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