PCF8536AT/1 View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

MFG CO.

PCF8536AT/1

Universal LCD driver for low multiplex rates including a 6 channel PWM generator

NXP Semiconductors. 

Prev 11 12 13 14 15 16 17 18 19 20 Next

NXP Semiconductors

PCF8536

Universal LCD low multiplex driver with 6 channel PWM generator

When EFR is set to 230 kHz, then the LCD frame frequency is calculated with Equation 2:

ffrLCD

=

f--c---l-k-----e--x--t--

48  q

(2)

where q is the frequency divide factor (see Table 21).

Remark: fclk(ext) is the external input clock frequency to pin OSCCLK.

When the internal oscillator is used, the intermediate frequency may be output on the

OSCCLK pin. Its frequency is given in Table 21.

Table 21. Frame frequency prescaler values for 230 kHz clock operation

FD[4:0]

Nominal LCD frame Divide factor, q

frequency (Hz)[1]

Intermediate clock

frequency (Hz)

0 0000

59.9

80

2 875

0 0001

70.5

68

3 382

0 0010

79.9

60

3 833

0 0011

90.4

53

4 340

0 0100

99.8

48

4 792

0 0101

108.9

44

5 227

0 0110

119.8

40

5 750

0 0111

129.5

37

6 216

0 1000

140.9

34

6 765

0 1001

149.7

32

7 188

0 1010

159.7

30

7 667

0 1011

171.1

28

8 214

0 1100

177.5

27

8 519

0 1101

191.7

25

9 200

0 1110[2]

199.7

24

9 583

0 1111

208.3

23

10 000

1 0000

217.8

22

10 455

1 0001

228.3

21

10 952

1 0010

239.6

20

11 500

1 0011

252.2

19

12 105

1 0100

266.2

18

12 778

1 0101

281.9

17

13 529

1 0110

299.5

16

14 375

10111 to 11111

not used

[1] Nominal frame frequency calculated for the default clock frequency of 230 kHz.

[2] Default value.

PCF8536

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 6 October 2011

© NXP B.V. 2011. All rights reserved.

17 of 74

Share Link: