PCF8536AT/1 View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

MFG CO.

PCF8536AT/1

Universal LCD driver for low multiplex rates including a 6 channel PWM generator

NXP Semiconductors. 

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NXP Semiconductors

PCF8536

Universal LCD low multiplex driver with 6 channel PWM generator

• the RAM columns and the segment outputs,

• the RAM rows and the backplane outputs.

The display RAM bit map, Figure 20, shows row 0 to row 7 which correspond with the

backplane outputs BP0 to BP7, and column 0 to column 43 which correspond with the

segment outputs S0 to S43. In multiplexed LCD applications, the data of each row of the

display RAM is time-multiplexed with the corresponding backplane (row 0 with BP0, row 1

with BP1, and so on).

When display data is transmitted to the PCF8536, the display bytes received are stored in

the display RAM in accordance with the selected LCD multiplex drive mode. The data is

stored as it arrives and depending on the current multiplex drive mode, data is stored in

quadruples, sextuples or bytes.

8.9.1 Data pointer (LCD part)

The addressing mechanism for the display RAM is realized using the data pointer. This

allows the loading of an individual display data byte, or a series of display data bytes, into

any location of the display RAM. The sequence commences with the initialization of the

data pointer by the load-data-pointer-LCD command (see Table 25).

Following this command, an arriving data byte is stored starting at the display RAM

address indicated by the data pointer.

The data pointer is automatically incremented in accordance with the chosen LCD

multiplex drive mode configuration. That is, after each byte is stored, the contents of the

data pointer are incremented

• by two (1:4 multiplex drive mode),

• by one or two (1:6 multiplex drive mode),

• by one (1:8 multiplex drive mode).

Multiplex drive 1:6 is a special case and is described later on.

When the address counter reaches the end of the RAM, it stops incrementing after the last

byte is transmitted. Redundant bits of the last byte and subsequent bytes transmitted are

discarded until the pointer is reset. To send new RAM data, the data pointer must be reset.

If an I2C-bus or SPI-bus data access is terminated early then the state of the data pointer

is unknown. The data pointer must then be re-written prior to further RAM accesses.

PCF8536

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 6 October 2011

© NXP B.V. 2011. All rights reserved.

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