PCF8536AT/1 View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

MFG CO.

PCF8536AT/1

Universal LCD driver for low multiplex rates including a 6 channel PWM generator

NXP Semiconductors. 

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NXP Semiconductors

PCF8536

Universal LCD low multiplex driver with 6 channel PWM generator

8.9.2 RAM filling in 1:4 multiplex drive mode

In the 1:4 multiplex drive mode the RAM is organized in four rows and 44 columns. The

eight transmitted data bits are placed in two successive display RAM columns of four rows

(see Figure 21). In order to fill the whole four RAM rows, 22 bytes need to be sent to the

PCF8536. After the last byte sent, the data pointer must be reset before the next RAM

content update. Additional data bytes sent and any data bits that spill over the RAM will be

discarded.

Columns

Display RAM addresses (columns)/segment outputs (S)

012 34 56 7

0 b7 b3

Rows

Display RAM

bits (rows)/

backplane outputs

(BP)

1 b6 b2

2 b5 b1

3 b4 b0

39 40 41 42 43

b7 b6 b5 b4 b3 b2 b1 b0

MSB

LSB

Transmitted data byte

013aaa455

Fig 21. Display RAM filling order in 1:4 multiplex drive mode

Depending on the start address of the data pointer, there is the possibility for a boundary

condition. This will occur when more data bits are sent than fit into the remaining RAM.

The additional data bits are discarded. See Figure 22.

Columns

Display RAM addresses (columns)/segment outputs (S)

Rows

Display RAM

bits (rows)/

backplane outputs

(BP)

012 34 56 7

0

1

2

3

39 40 41 42 43

b7

b6

b5

b4

Discarded

Fig 22. Boundary condition in 1:4 multiplex drive mode

b7 b6 b5 b4 b3 b2 b1 b0

MSB

LSB

Transmitted data byte

013aaa456

PCF8536

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 6 October 2011

© NXP B.V. 2011. All rights reserved.

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