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PCF8536AT/1 View Datasheet(PDF) - NXP Semiconductors.

Part Name
Description
MFG CO.
'PCF8536AT/1' PDF : 74 Pages View PDF
NXP Semiconductors
PCF8536
Universal LCD low multiplex driver with 6 channel PWM generator
8.9.4 RAM filling in 1:8 multiplex drive mode
In the 1:8 multiplex drive mode the RAM is organized in eight rows and 40 columns. The
eight transmitted data bits are placed into eight rows of one display RAM column (see
Figure 25). In order to fill the whole RAM, 40 bytes need to be sent to the PCF8536. After
the last byte sent, the data pointer must be reset before the next RAM content update.
Additional data bytes sent will be discarded.
Columns
Display RAM columns/segment outputs (S)
012 34 56 7
0 b7
1 b6
Rows
Display RAM rows/
backplane outputs
(BP)
2 b5
3 b4
4 b3
5 b2
6 b1
7 b0
35 36 37 38 39
b7 b6 b5 b4 b3 b2 b1 b0
MSB
LSB
Transmitted data byte
013aaa459
Fig 25. Display RAM filling order in 1:8 multiplex drive mode
There are no boundary conditions in 1:8 multiplex drive mode.
8.10 PWM registers and data pointer (PWM part)
There are six PWM generators which can be independently configured. The values used
to define the PWM output are stored here.
The addressing mechanism for the PWM register is realized using the PWM data pointer.
This allows the loading of an individual PWM data byte, or a series of data bytes, into any
location of the PWM registers. The sequence commences with the initialization of the data
pointer by the load-data-pointer-PWM command (see Table 26).
Following this command, an arriving data byte is stored starting at the PWM register
address indicated by the PWM data pointer. The data pointer is automatically
incremented. That is, after each byte is stored, the contents of the data pointer are
incremented. The data pointer will wrap around continuously as long as data is
transmitted.
PCF8536
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 6 October 2011
© NXP B.V. 2011. All rights reserved.
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