PI6CV857
PLL Clock Driver
for 2.5V DDR-SDRAM Memory 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
Electrical Characteristics
Parameter
Test Conditions
VIK All inputs
VOH High output voltage
VOL Low output voltage
II = –18mA
IOH = –100μA
IOH = –14mA
IOL = 100μA
IOL = 14mA
II
IDDQ
IADD
CK, FBIN
PWRDWN
Dynamic supply current of VDDQ
Static supply current
Dynamic supply current of AVDD
Static supply current
VI = VDDQ or GND
VI = VDDQ or GND
VDD = 2.7V (1)
CK & CK <20 MHz or
PWRDWN = Low (2)
VDD = 2.7V (1)
CK & CK <20 MHz or
PWRDWN = Low (2)
CK and CK
CI
FBIN and FBIN
VI = VDD or GND
AVDD, VDDQ
Min.
Typ. Max. Units
2.3V
–1.2
2.3V to 2.7V VDDQ –0.1
2.3V
1.7
V
2.3V to 2.7V
0.1
2.3V
0.6
±10 μA
2.7V
300 mA
100 μA
12 mA
100 μA
2.5V
2.0
3.0 pF
Notes:
1. Driving 9 or 18 DDR SDRAM memory chips with 120-ohm termination resistor for each clock output pair at 134 MHz.
2. The maximum power down clock frequency is below 20 MHz.
08-0298
5
PS8464F
11/06/08