PI6CV857 View Datasheet(PDF) - Pericom Semiconductor
Part Name
Description
MFG CO.
'PI6CV857' PDF : 10 Pages View PDF
PI6CV857
PLL Clock Driver
for 2.5V DDR-SDRAM Memory 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
AC Specifications
Switching characteristics over recommended operating free-air temperature range (unless otherwise noted)
Parameter
Description
tjit(cc)
t(θ)
tsk(o)
tjit(per)
tjit(hper)
tsl(i)
tsl(o)
Cycle-to-cycle jitter
Static phase offset(1)
Output clock skew
Period jitter
Half-period jitter
Input clock slew rate(2)
Output clock slew rate(2)
Diagram
see Figure 3
see Figure 4
see Figure 5
see Figure 6
see Figure 7
see Figure 8
see Figure 8
AVDD, VDDQ = 2.5V ±0.2V
Min.
Nom.
Max
–75
75
–50
0
50
100
–75
75
–100
100
1.0
2.0
1.0
2.0
Units
ps
V/ns
The PLL on PI6CV857 meets the above parameters while supporting SSC synthesizers with the following parameters(3).
SSC modulation frequency
SSC clock input frequency deviation
PLL loop bandwidth
Phase angle
30.00
0.00
50.00
–0.50
2
–0.031
Notes:
1. Static Phase offset does not include Jitter.
2. The slew rate is determined from the IBIS model and not from the test load.
3. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification.
kHz
%
MHz
degrees
08-0298
6
PS8464F
11/06/08
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