PI6CV857
PLL Clock Driver
for 2.5V DDR-SDRAM Memory 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
Yx,FBOUT
Yx,FBOUT
tcycle n
tcycle n+1
tjit(cc) = tcycle n - tcycle n+1
Figure 3. Cycle-to-Cycle Jitter
CK
CK
FBIN
FBIN
t( ) n
t=
n=N
1 t( ) n
N
t( ) n+1
(N is a large number of samples)
Figure 4. Static Phase Offset
Yx
Yx
Yx, FBOUT
Yx, FBOUT
t sk(o)
Figure 5. Output Skew
08-0298
8
PS8464F
11/06/08