PI6CV857
PLL Clock Driver
for 2.5V DDR-SDRAM Memory 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
Yx, FBOUT
Yx, FBOUT
Yx, FBOUT
Yx, FBOUT
tcycle n
1
fO
t jit(per) = t cycle n
1
fO
Figure 6. Period Jitter
Yx, FBOUT
Yx, FBOUT
thalf period n
1
fO
t n+1
half period
t jit(hper) = t half period n
1
2*fO
Figure 7. Half-Period Jitter
80%
20%
Clock Inputs
and Outputs
t sl(i), t sl(o)
t sl(i), t sl(o)
80%
V ID
20%
Figure 8. Input and Output Slew Rates
08-0298
9
PS8464F
11/06/08