PM5343STXC View Datasheet(PDF) - PMC-Sierra
Part Name
Description
MFG CO.
'PM5343STXC' PDF : 198 Pages View PDF
DATA SHEET
PMC-930303
ISSUE 6
PM5343 STXC
SONET/SDH TRANSPORT OVERHEAD TRANSCEIVER
8 PIN DESCRIPTION
Pin Name Pin Type Pin Function
No.
RSER
Input
RICLK/
Input
RVCLK
RIN[7]
RIN[6]
RIN[5]
RIN[4]
RIN[3]
RIN[2]
RIN[1]
RIN[0]
Input
Input
Input
Input
Input
Input
Input
Input
52 The receive serial input (RSER) selects the
receive line interface. RSER is tied high to
select the bit serial interface on PECL pins
RXC+, RXC-, RXD+, and RXD-. A TTL
interface is also supported in STS-1 mode on
pins RSIN and RSICLK. RSER is tied low to
select the byte serial interface (on pins RICLK,
RIN[7:0], and RIFP).
135 The receive incoming clock (RICLK) provides
timing for processing the byte serial receive
stream, RIN[7:0]. RICLK is nominally a 6.48
MHz (STS-1), or 19.44 MHz (STS-3/STM-1)
50% duty cycle clock, depending on the
selected operating mode. RIN[7:0], and RIFP
are sampled on the rising edge of RICLK.
RICLK must be externally shorted directly to
GRICLK when processing a bit serial receive
stream.
The receive vector clock (RVCLK) is used
during STXC production test to verify internal
functionality.
51 The receive incoming stream (RIN[7:0]) carries
49
the scrambled STS-1 or STS-3/STM-1 stream
in byte serial format. RIN[7] is the most
48 significant bit (corresponding to bit 1 of each
47 serial PCM word, the first bit transmitted).
RIN[0] is the least significant bit (corresponding
46 to bit 8 of each serial PCM word, the last bit
44 transmitted). RIN[7:0] is sampled on the rising
edge of RICLK.
43
42
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 10
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