PM5343STXC View Datasheet(PDF) - PMC-Sierra
Part Name
Description
MFG CO.
'PM5343STXC' PDF : 198 Pages View PDF
DATA SHEET
PMC-930303
ISSUE 6
PM5343 STXC
SONET/SDH TRANSPORT OVERHEAD TRANSCEIVER
Pin Name Pin Type Pin Function
No.
RIFP
RSIN
Input
Input
41 The active high receive incoming framing
position (RIFP) signal indicates when the first
byte of the synchronous payload envelope is
available on the RIN[7:0] inputs. RIFP is
sampled on the rising edge of RICLK.
53 The receive incoming serial stream (RSIN)
contains the TTL compatible 51.84 Mbit/s
receive STS-1 stream. RSIN is sampled on the
rising edge of RSICLK. The RSIN input has an
integral pull down resistor. The RXD+/- inputs
may also carry the receive STS-1 stream.
RSICLK Input
54 The receive serial incoming clock (RSICLK)
provides timing for processing the bit serial
receive stream, RSIN when the TTL bit serial
STS-1 mode is selected. RSICLK is nominally
a 51.84 MHz, 50% duty cycle clock. RSIN is
sampled on the rising edge of RSICLK.
RSICLK is divided by eight to produce GRICLK
when the TTL bit serial STS-1 mode is
selected. The RSICLK input has an integral
pull down resistor.
RXD+
RXD-
RXC+
RXC-
PECL
Input
PECL
Input
63 The receive differential data inputs (RXD+,
62 RXD-) contain the 155.52 Mbit/s receive STS-
3/STM-1 or 51.84 Mbit/s receive STS-1 stream.
RXD+/- is sampled on the rising edge of
RXC+/- (the falling edge may be used by
reversing RXC+/-).
59 The receive differential clock inputs (RXC+,
58 RXC-) provides timing for processing the bit
serial receive stream, RXD+/- when the PECL
bit serial mode is selected. RXC+/- is
nominally a 155.52 MHz or 51.84 MHz, 50%
duty cycle clock. RXD+/- is sampled on the
rising edge of RXC+/-. RXC+/- is divided by
eight to produce GRICLK when the PECL bit
serial mode is selected.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 11
Share Link: 
