PM5343STXC View Datasheet(PDF) - PMC-Sierra
Part Name
Description
MFG CO.
'PM5343STXC' PDF : 198 Pages View PDF
DATA SHEET
PMC-930303
ISSUE 6
PM5343 STXC
SONET/SDH TRANSPORT OVERHEAD TRANSCEIVER
Pin Name Pin Type Pin Function
No.
RDI/
Output
RRCPCLK
73 The far end receive failure (RDI) signal is active
when the ring control port is disabled. RDI is
set high when line RDI is detected in the
incoming stream. RDI is declared when a 110
binary pattern is detected in bits 6, 7, and 8 of
the K2 byte for three or five consecutive
frames. RDI is removed when any pattern
other than 110 is detected in bits 6, 7, and 8 of
the K2 byte for three or five consecutive
frames. This alarm indication is also available
through register access. RDI is updated on the
rising edge of RICLK.
The receive ring control port clock (RRCPCLK)
signal provides timing for the receive ring
control port when the ring control port is
enabled (the enabling and disabling of the ring
control port is controlled by a bit in the Master
Control Register). RRCPCLK is nominally a
3.24 MHz, 50% duty cycle clock and is
normally connected to the TRCPCLK input of a
mate STXC in ring-based add-drop multiplexer
applications. RRCPFP and RRCPDAT are
updated on the falling edge of RRCPCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 14
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