PM5343STXC View Datasheet(PDF) - PMC-Sierra
Part Name
Description
MFG CO.
'PM5343STXC' PDF : 198 Pages View PDF
DATA SHEET
PMC-930303
ISSUE 6
PM5343 STXC
SONET/SDH TRANSPORT OVERHEAD TRANSCEIVER
Pin Name Pin Type Pin Function
No.
LAIS/
Output
RRCPDAT
72 The line alarm indication (LAIS) signal is active
when the ring control port is disabled. LAIS is
set high when line AIS is detected in the
incoming stream. LAIS is declared when a 111
binary pattern is detected in bits 6, 7, and 8 of
the K2 byte for three or five consecutive
frames. LAIS is removed when any pattern
other than 111 is detected in bits 6, 7, and 8 of
the K2 byte for three or five consecutive
frames. This alarm indication is also available
through register access. LAIS is updated on
the rising edge of RICLK.
The receive ring control port data (RRCPDAT)
signal contains the receive ring control port
data stream when the ring control port is
enabled (the enabling and disabling of the ring
control port is controlled by a bit in the Master
Control Register). The receive ring control port
data consists of the filtered K1, K2 byte values,
the change of APS value bit position, the
protection switch byte failure status bit position,
the send AIS and send RDI bit positions, and
the line REI bit positions. RRCPDAT is
normally connected to the TRCPDAT input of a
mate STXC in ring-based add-drop multiplexer
applications. RRCPDAT is updated on the
falling edge of RRCPCLK.
B2E
Output
RSDCLK Output
78 The B2 error clock (B2E) is a return to zero
signal that pulses 154 ns with a minimum low
time of 154 ns for every line bit interleaved
parity error (B2) detected in the incoming
stream. Up to 8 (STS-1), or 24 (STS-3/STM-1)
pulses may occur on B2E, per frame.
67 The receive section DCC clock (RSDCLK) is a
192 kHz clock used to update the RSD output.
RSDCLK is generated by gapping a 216 kHz
clock.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 15
Share Link: 
