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PM7382-PI View Datasheet(PDF) - PMC-Sierra

Part Name
Description
MFG CO.
'PM7382-PI' PDF : 330 Pages View PDF
RELEASED
DATA SHEET
PMC-2010333
ISSUE 3
PM7382 FREEDM-32P256
FRAME ENGINE AND DATA LINK MANAGER 32P256
7 PIN DESCRIPTION
Table 1 – Line Side Interface Signals (154)
Pin Name Type
RCLK[0]
RCLK[1]
RCLK[2]
RCLK[3]
RCLK[4]
RCLK[5]
RCLK[6]
RCLK[7]
RCLK[8]
RCLK[9]
RCLK[10]
RCLK[11]
RCLK[12]
RCLK[13]
RCLK[14]
RCLK[15]
RCLK[16]
RCLK[17]
RCLK[18]
RCLK[19]
RCLK[20]
RCLK[21]
RCLK[22]
RCLK[23]
RCLK[24]
RCLK[25]
RCLK[26]
RCLK[27]
RCLK[28]
RCLK[29]
RCLK[30]
RCLK[31]
Input
Pin Function
No.
N23 The receive line clock signals (RCLK[31:0])
N21 contain the recovered line clock for the 32
M22 independently timed links. Processing of the
L21 receive links are on a priority basis, in
L20 descending order from RCLK[0] to RCLK[31].
K22 Therefore, the highest rate link should be
J22 connected to RCLK[0] and the lowest to
J23 RCLK[31].
G21
G20
F22
F21
E21
D23
D21
C21
B22
A21
For channelised T1/J1 or E1 links, RCLK[n]
must be gapped during the framing bit (for T1/J1
interfaces) or during time-slot 0 (for E1
interfaces) of the RD[n] stream. The FREEDM-
32P256 uses the gapping information to
determine the time-slot alignment in the receive
stream. RCLK[31:0] is nominally a 50% duty
cycle clock of frequency 1.544 MHz for T1/J1
links and 2.048 MHz for E1 links.
C20 For unchannelised links, RCLK[n] must be
A20 externally gapped during the bits or time-slots
C19 that are not part of the transmission format
C18 payload (i.e. not part of the HDLC packet).
B18 RCLK[2:0] is nominally a 50% duty cycle clock
D17 between 0 and 51.84 MHz. RCLK[31:3] is
B16 nominally a 50% duty cycle clock between 0 and
A15 10 MHz.
B15 The RCLK[n] inputs are invalid and should be
A14 forced to a low state when their associated link
C14 is configured for operation in H-MVIP mode.
A13
C13
B12
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 11
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