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PM7382-PI View Datasheet(PDF) - PMC-Sierra

Part Name
Description
MFG CO.
'PM7382-PI' PDF : 330 Pages View PDF
RELEASED
DATA SHEET
PMC-2010333
ISSUE 3
PM7382 FREEDM-32P256
FRAME ENGINE AND DATA LINK MANAGER 32P256
Pin Name Type Pin
No.
RMV8DC Input R22
RBD
Tristate R23
Output
RBCLK
Tristate R20
Output
Function
The receive 8.192 Mbps H-MVIP data clock
signal (RMV8DC) provides the receive data
clock for links configured to operate in 8.192
Mbps H-MVIP mode.
RMV8DC is used to sample data on RD[4m]
(0£m£7) when link 4m is configured for 8.192
Mbps H-MVIP operation. RMV8DC is nominally
a 50% duty cycle clock with a frequency of
16.384 MHz.
RMV8DC is ignored and should be tied low
when no physical links are configured for
operation in 8.192 Mbps H-MVIP mode.
The receive BERT data signal (RBD) contains
the receive bit error rate test data. RBD reports
the data on the selected one of the receive data
signals (RD[31:0]) and is updated on the falling
edge of RBCLK. RBD may be tristated by
setting the RBEN bit in the FREEDM-32P256
Master BERT Control register low. BERT is not
supported for H-MVIP links.
The receive BERT clock signal (RBCLK)
contains the receive bit error rate test clock.
RBCLK is a buffered version of the selected one
of the receive clock signals (RCLK[31:0]).
RBCLK may be tristated by setting the RBEN bit
in the FREEDM-32P256 Master BERT Control
register low. BERT is not supported for H-MVIP
links.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 15
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