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PM7382-PI View Datasheet(PDF) - PMC-Sierra

Part Name
Description
MFG CO.
'PM7382-PI' PDF : 330 Pages View PDF
RELEASED
DATA SHEET
PMC-2010333
ISSUE 3
PM7382 FREEDM-32P256
FRAME ENGINE AND DATA LINK MANAGER 32P256
Pin Name Type
RMVCK[0]
RMVCK[1]
RMVCK[2]
RMVCK[3]
Input
RFPB[0]
RFPB[1]
RFPB[2]
RFPB[3]
Input
Pin Function
No.
P21 The receive MVIP data clock signals
H22 (RMVCK[3:0]) provide the receive data clock for
A23 the 32 links when configured to operate in 2.048
C17 Mbps H-MVIP mode.
When configured for 2.048 Mbps H-MVIP
operation, the 32 links are partitioned into 4
groups of 8, and each group of 8 links share a
common data clock. RMVCK[0], RMVCK[1],
RMVCK[2] and RMVCK[3] sample the data on
links RD[7:0], RD[15:8], RD[23:16] and
RD[31:24] respectively. Each RMVCK[n] is
nominally a 50% duty cycle clock with a
frequency of 4.096 MHz.
RMVCK[n] is ignored and should be tied low
when no physical link within the associated
logical group of 8 links is configured for
operation in 2.048 Mbps H-MVIP mode.
P22 The receive frame pulse signals (RFPB[3:0])
H21 reference the beginning of each frame for the 32
B23 links when configured for operation in 2.048
B17 Mbps H-MVIP mode.
When configured for 2.048 Mbps H-MVIP
operation, the 32 links are partitioned into 4
groups of 8, and each group of 8 links share a
common frame pulse. RFPB[0], RFPB[1],
RFPB[2] and RFPB[3] reference the beginning
of a frame on links RD[7:0], RD[15:8], RD[23:16]
and RD[31:24] respectively.
When configured for operation in 2.048 Mbps H-
MVIP mode, RFPB[n] is sampled on the falling
edge of RMVCK[n]. Otherwise, RFPB[n] is
ignored and should be tied low.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 13
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